Vijaykrishnan Narayanan

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Postdoctoral Research Alumni

2007-08. Currently Professor at Indian Institute of Technology, Madras

Postdoctoral Researcher and Ph.D. Alumni

2009-16, Research Associate, Smart Camera Systems

Ph.D./CSE, A Configurable Platform for Sensor and Image Processing (Awarded Bunton-Waller and Alfred Sloan Fellowship during Ph.D.) (MDL)

MS/CSE, Embedded Face Detection, May 2005

Postdoctoral Researcher and Ph.D. Student at Penn State

2011, Research Associate, Configurable Systems

Ph.D./CSE, Configurable Accelerators for Video Analytics (co-advised with Dr. Xie)

Currently at IBM, Almaden

Postdoctoral Researcher at MDL

2010, Research Associate, Biologically Inspired Vision Systems

Postdoctoral Researher at MDL

2010-11, Post Doctoral Student, Custom Accelerators

Ph.D. Alumni

Ph.D./CSE, Energy-Aware Hardware and Software Optimizations, August 2004 (Samsung Electronics, Korea) (co-advised with Dr. Irwin)

Ph.D. Alumni

Ph.D./CSE, High Performance and Low Power Cache Architectures, December 2003 (Associate Professor, KAIST, Korea)

Ph.D. Alumni

Ph.D./CSE, Architectural and Compiler Support for Energy Efficient Caches, August 2004 (Intel, Portland)

Ph.D. Alumni

Ph.D./CSE, Designing Energy Efficient and Reliable Caches and Interconnects, August 2005 (Intel, Portland)(co-advised with Dr. Irwin)

Ph.D. Alumni

Ph.D./CSE, Leakage Energy Modeling, August 2005 (Microsemi, Taiwan)

Ph.D. Alumni

Ph.D/CSE, Soft Errors; Modeling and Interactions with Power Optimizations, August 2005 (Intel, Bangalore)

Ph.D. Alumni

Ph.D./CSE, Security issues in embedded systems, August 2005 (co-advised with Dr.Kandemir)(Institute of Information Research, Singapore)

Ph.D. Alumni

Ph.D/CSE, Application Specific Multiprocessor Systems on Chip, December 2005 (University of Cyprus)

Ph.D. Alumni

Ph.D./EE, VLSI Architectures for Video Processing, August 2006 (co-advised with Dr. Jenkins, Electrical Engineering) (Hongik University, South Korea)

Ph.D. Alumni

Ph.D./CSE, Thermal Issues in Next Generation Microprocessors, August 2006 (Awarded CAC Fellowship during Ph.D.) (University of York)

Ph.D. Alumni

Ph.D./CSE, Power-Aware FPGAs, Dec 2006 (co-advised with Dr. Kandemir) (Synopsys)

Ph.D. Alumni

Ph.D./CSE, Secure Embedded and Mobile Systems (Motorola)

Ph.D. Alumni

Ph.D./EE, Soft Errors in Logic and Memory Systems (Intel, Bangalore)

Ph.D. Alumni

Ph.D./CSE, High-Level Power and Reliability Estimation (co-advised with Dr. Irwin) (NCKU, Taiwan)

Ph.D. Alumni

Ph.D./CSE, Power-Aware Robust FPGA Systems, 2007 (Intel, Bangalore)

Ph.D. Alumni

Ph.D./EE, Architectural Innovations for for On Chip Networks (University of Cyprus) 2008 EDAA Outstanding Dissertation Award (co-advised with K. Jenkins)

Ph.D. Alumni

Ph.D./EE, Algorithm-Architecture Co-Design for Signal Processing Systems (Samsung)

Ph.D. Alumni

Ph.D./CSE, Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems. (Availink Inc)

Ph.D. Alumni

Ph.D./EE, Analyzing Failures in Nanoscale Devices (co-advised with Dr. Suman Datta) (TSMC, Taiwan)

Ph.D. Alumni

Ph.D./CSE, A Reliability and Process Variation Aware Design flow for Platform FPGAS (Co-advised with Dr. Xie) (Intel, Santa Clara)

Ph.D. Alumni

Ph.D./CSE, FPGA Architectures in Emerging Technologies (co-advised with Dr. Yuan Xie) (Intel, Portland)

Ph.D. Alumni

Ph.D./CSE, Reliability-Power Tradeoffs in On-Chip Networks (co-advised with Dr. Irwin) (Intel, Portland)

Ph.D. Alumni

Ph.D./CSE, Closing the gap between FPGAs and ASICs: The applications of clock skew scheduling to FPGA (Samsung, Korea)

Ph.D. Alumni

Ph.D./CSE, Analyzing Architectural Vulnerability Factor (co-advised with Dr. Sivasubramaniam) (Intel, Portland)

Ph.D. Alumni

Ph.D./CSE, Device and Architecture Co-Design for Ultra-Low Power Logic Using Emerging Tunneling-Based devices (Co-advised with Dr. S. Datta) (Intel, Santa Clara)

Ph.D. Alumni

Ph.D./EE, Automated Generation of Signal Processing Systems (co-advised with Dr. Datta)(Google)

Ph.D. Alumni

Ph.D./CSE, Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems (ETRI, Taiwan)

Ph.D. Alumni

Ph.D./CSE, Accelerating Design and Implementation of Embedded Vision Systems (Sultan Qaboos University, Oman)

Ph.D. Alumni

Ph.D./CSE, Leveraging Reconfigurable Architectures for Large Scale Real-time Video Analytics (Intel, Sacremento).

Ph.D. Alumni

Ph.D./CSE, SUB-50 NM MULTI-SEGMENT INTERCONNECT DESIGN: A TREATISE ON SPEED, RELIABILITY AND SIGNAL INTEGRITY.

Ph.D. Alumni

Ph.D./CSE, Configurable Architectures (Intel)

Ph.D. Alumni

Ph.D./CSE, Object Recognition Architectures (Synopsys)

Ph.D. Alumni

Ph.D./CSE, An examination of architectures using Steep Slope devices (IBM Watson)

Ph.D. Alumni

Ph.D./CSE, Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory (Co-Advised with Dr. Yuan Xie)

Ph.D. Alumni

Ph.D./EE, Low Power Devices and Circuit Interactions (Intel)

Ph.D. Alumni

Ph.D./CSE, Enabling Intelligent Vision Systems in a Configurable Multi-Algorithm Pipeline (Applied Research Labs)

Ph.D. Alumni

Ph.D./CSE, Large-Scale Object Recognition for Embedded Wearable Platforms (Samsung Research)

Ph.D. Alumni

Ph.D./CSE, Digital/Mixed-Signal Circuit Designs With Steep Slope Tunnel Transistors (Intel, Sacremento)

Ph.D. Alumni

 Ph.D./CSE, Data Dependent Optimization Vision Architecture

Ph.D. Alumni

Ph.D./CSE, Heterogenous Multiprocessor Architectures (IBM Watson)

MS Alumni

MS/CSE, Memory System Characterization of Java Applications, May 2000 (at Helwett Packard, Bay Area)

MS Alumni

MS/CSE, Annotation Based Energy Optimization for Java, December 2000 (at Dell, Austin)

MEng Alumni

MS/CSE, Protecting Java Applications Against Decompilation via Control Flow Obfuscation, December 2000 (At IBM, Pittsburgh)

 MS/CSE, Characterizing and Optimizing Memory Energy in Java, May 2001

MS/CSE, Power Modeling and Optimization of Memories and Functional Units , May 2001 (co-advised with Dr. Irwin) (CTO at DigicomCore, Laussane)

MS/CSE, Low Power Content Addressable Memory Design, May 2001 (US Patent and Trademark Office)

MS/CSE, Improving ILP with Instruction Reuse Cache Hierarchy, May 2001 (Co-advised with Dr. Hurson) (at PMC-Sierra)

MS/CSE, Influence of MPEG-4 Parameters on System Energy, August 2001 (at Synospys, CA)

MEng/CSE, Implementation of a Java Accelerator:  Interfacing the Java Virtual Machine with the FPGA, August 2001

MS/CSE, Memory Energy Characterization and Optimization of SPEC2000 Benchmarks, December 2001 (co-advised with Dr. Sivasubramaniam)

MS/CSE, OS Paging Issues for DRAM Energy Management, December 2001 (Co-advised with Dr. Sivasubramaniam)

MS/CSE, Evaluating Energy-Efficiency of Channel Coders, May 2002 (co-advised with Dr. Irwin)

MS/CSE, Compiler-directed Voltage Scaling for Reducing Energy, December 2001 (co-advised with Dr. Kandemir)

MS/CSE, Characterization and Modeling for Run-time Leakage Reduction Techniques, December 2002 (co-advised with Dr. Irwin)

MS/CSE, Leakage Power Estimation Tool for CMOS Circuits, May 2003 (co-advised with Dr. Irwin) (with Cyprus Semiconductors, India)

MS/CSE, Variable Line Sized Cached DRAM, August 2003 (Software Consultant, NY)

MEng/CSE, Analyzing the Common Language Runtime, August 2003 (co-advised with Dr. Saraswat) (at SMG Inc.)

MS/CSE, A Workload Characterization and Performance Analysis of Multiprocessor Immersive Display Environments, December 2003 (at Lockheed Martin, Valley Forge)

MS/CSE, Encryption and Security in SRAM FPGAs, May 2004 (at Naval Research Labs)

MS/CSE, Leakage control mechanism for FPGAs, August 2004

MS/CSE, Soft error analysis of CAMs, August 2004 (Intel)

MS/CSE, On-Chip Interconnects, Dec 2005 (co-advised with Y. Xie) (Availink, Inc.)

MS/CSE, Mapping Signal Processing Applications on FPGAs, Dec 2006 (Availink, Inc.)

M.S./CSE, Performance Evaluation of SystemC and Verilog for RTL Synthesis and System Modeling, December 2006 (Intel)

M.S./CSE, Static and Runtime Optimization Strategies for Variation Aware MPSoC Platforms, December 2006 (Cisco)

M.S./CSE, Thermal-Aware Placement and Variation for Three Dimensional Network-on-Chip Designs, May 2007 (Co-advised with Prof. Xie) (Penn State)

M.S./CSE, Impact of Circuit Degradation on Design Security of Field programmable Devices, August 2007 (Co-advised with Prof. Xie) (Mahamedi Paradice Kreisman LLP, San Jose)​

M.S./CSE, Performance-Reliability Tradeoffs in designing reorder buffers, May 2008 (Ph.D. student at U.Wisconsin)

M.S./CSE, Variation-aware CAM structures, Dec 2008 (Deceased)

M.S./CSE, A Signal Based Approach to an Instrument Driver System, Dec 2008 (Lockheed Martin)

MS/EE, A Neural Network Based Classifier on Cell Broadband Engine, May 2009 (co-advised with Dr. Datta) (Ph.D. Student at U. Tennessee)

MS/EE, A GPU based implementation of Center Surround Distribution Distance Algorithm for feature recognition, Dec 2009 (co-advised with Dr. Jenkins) (Tata Computational Research Labs, India)

MS/EE, Connected Component Labeling on FPGAs, May 2010 (Samsung, Korea)

MS/CSE, FPGA based Image recognition, Dec 2010 (Heatfusion)

MS/EE, Accelerating Image Saliency on FPGAs (PMC Sierra, Allentown)

MS/CSE, TFET Based FPGA (Intel)

MS/EE, A Fine-Grained Dataflow Library for Reconfigurable Streaming Accelerators (Intel)​

MS/CSE, A Game Theoretic Approach To Multi-Agent Systems In Highly Dynamic, Information-Sparse, Role Assignment Scenarios  (ARL)

MS/CSE, Depth Estimation using monocular cameras

MS/CSE, A Reconfigurable Accelerator For Neuromorphic Object Recognition

MS/CSE, Prediction and assessment of ambient energy signals for energy harvesting systems

BS (Honors), Charge Recovery Buses, May 2000 (at AMD, Austin)

BS (Honors), Performance Tradeoffs in Client Server Partitioning of Java Applications, May 2003 (Compunetix, Pittsburgh)

BS (Honors), Dynamic Web Design for Multiple Platforms, May 2003 (IBM, Research Triangle)

BS (Honors), Soft errors in memories, May 2005 (Naval Research Lab)

BS (Honors), Interfacing Multi FPGA Platforms, Spring 2007. (IBM., Research Triangle)

BS (Honors), FPGA-based LADAR Control System, May 2009

MS/BS Honors, improving object recognition performance through semantic context extraction

MS/BS(Honors), Optimization and Hardware Acceleration of Consensus-based Matching and Tracking